The present invention relates to a data conversion chart for converting serial data to parallel data or for converting parallel data to serial data.
The data conversion circuit of this kind is generally constructed using a shift register. The shift register is initiated into operation with clock signals supplied to each flip-flop of which the shift register is made up.
The transmission lines for the clock signals to each flip-flop, however, have some stray capacitance or the like. The clock signals are therefore transmitted with some delay so that the flip-flops in the shift register cannot operate in completely precise synchronization with each other.
FIG. 1 shows a serial to parallel data conversion circuit according to a prior art. The data conversion circuit converst a serial signal ST into respective parallel signals Q1, Q2, Q3 and Q4, and master/slave flip-flops F10, FF20, FF30 and FF40 are provided each in correspondence with particular bit of the parallel signals. A more detailed circuit construction of each of the flip-flops is shown in FIG. 1A, and in FIG. 1B a more concrete version thereof is shown. The master/slave flip-flops FF10, FF20, FF30, and FF40 comprise master flip-flops FF11, FF21, FF31 and FF41, and slave flip-flops FF12, FF22, FF32 and FF42. The master flip-flops and slave flip-flops each comprise a transfer gate TC and an inverter I, the master flip-flop being supplied with a clock CLK as its input, and the slave flip-flop with a clock CLK. Each flip-flop is constructed as shown in FIG. 1B, with a MOS logic circuit. In the logic circuit, the transfer gate TG is made of a single MOS FET, and the inverter I is made of a pair of P and N-channel MOS FETs, that is, Q.sub.11, Q.sub.12 and Q.sub.21, Q.sub.22.
The description given hereinbelow is made by using the symbols depicted in FIG&gt;1 or FIG. 1A for the purpose of convenience for drawing figures. Note that each flip-flop, corresponding to a respective master or slave flip-flop, has not only the transfer gate TG and inverter I, but also a stray capacitance CG as well, as shown in FIG. 2.
The operation of the conventional shift register is discussed with reference to FIG. 3. The input of a serial signal SI passes through the flip-flop FF11 during the time when a clock signal CLK takes an H level to thereby deliver an output Qa, which is applied to an input terminal D of the flip-flop FF12. The data of the flip-flop FF11 is held by the stray capacitance Cg after the clock signal CLK turns to an L level. At the same time in response to the clock signal CLK inverted by the inverter INV, the flip-flop FF12 outputs the data which has been held by the flip-flop FF11. Similarly to the above, in the master/slave flip-flops FF20, FF30 and FF40, the input of the serial signal SI is successively transferred to and held at respective flip-flops FF21, FF22, FF31, FF32, FF41 and FF42 which constitute the master/slave flip-flops, in synchronization with the clock signal CLK. Thus, an output of parallel signals Q1, Q2, Q3 and Q4 is obtained.
With the shift register described above, there has been some problems, however, in that a so-called race phenomenon occurs due to a time delay caused by a wiring in the integrated circuit of the inverter. More particularly, reference is made to FIG. 4 which is a portion of an equivalent circuit to FIG. 1 and is depicted by placing particular emphasis upon the clock signals CLK, CLK. The transmission lines of the clock signals CLK, CLK contain wiring resistances R1, R2, R3, R4 and stray capacitances C1, C2, C3, C4, which cause a signal delay. Therefore, a phase delay of .DELTA.t arises between the clock signals CLK and CLK, as shown in FIG. 5. Thus, a time duration exists during which both clock signals CLK and CLK matinain H level, so that the output Qb of the inverter I3 is transferred to the inverter I4 to change its output Q2 without being interrupted by the transfer gate TG4. A tunneling phenomenon between inverters occurs which is generally called a race phenomenon.